Device and a method for testing disconnection by grouping bus lines of a semiconductor device

ABSTRACT

A device for testing for disconnection of bus lines of a semiconductor device includes switches having current ratios formed in a geometric series connected to ends of a group of n of the bus lines. At least one testing electrode is connected to the switches and at least one power electrode is connected to the group of n of the bus lines. A disconnection of one or more of the bus lines can be determined according to a current flowing through the testing electrode.

BACKGROUND OF THE INVENTION

1 . Field of the Invention

The present invention relates to a device and a method for testingdisconnection of bus lines of a semiconductor device. More particularly,it relates to a device and a method for testing disconnection bygrouping bus lines of a semiconductor device to find disconnected buslines by grouping by n units bus lines to which switching devices whosecurrent ratios from a geometric series are connected and measuring a sumof the current flowing through the bus lines grouped by n units whentesting disconnection of a semiconductor device having bus lines asdynamic random access memory (DRAM), static random access memory (SRAM),liquid crystal display panel and the like.

2. Description of the Prior Art

Tests of disconnection or short of bus lines are performed whenmanufacturing semiconductor devices having bus lines (or electrodelines) as DRAM, SRAM, liquid crystal display panel, and the like.

FIG. 3 is a circuit diagram showing a method for testing disconnectionof bus lines of a semiconductor device according to a conventional art.

A liquid crystal panel 30 is shown in FIG. 3, and there are formedelectrodes DPAD, GPAD for applying test voltage respectively on an upperarea in a column and on a left side in a row, and electrodes D1 to Djand G1 to Gi for detecting current respectively on a lower area in acolumn and on a right side in a row.

The test determining whether the bus lines of the liquid crystal panel30 are disconnected or not is performed by applying test voltage to theelectrodes DPAD and GPAD on the upper area and the left side of theliquid crystal display panel 30, and testing whether the current isdetected or not from the electrodes G1 to Gi and D1 to Dj on the lowerarea and the right side.

However, according to the conventional art, since each bus line of thesemiconductor should have one testing electrode although the number ofbus lines increases, spaces between the bus lines narrow, and wherebythe bus lines have high density, the testing time increases and itbecomes difficult to test minutely. Such a problem is more serious in aliquid crystal display panel that has a plurality of bus lines.

Korean Patent Publication Nos. 93-3670, 93-3672, and 93-7162 providerespectively a device for testing an indium tin oxide (ITO) electrode ofa flat panel device, a method and a device for testingdisconnection-short of a transparent electrode of a liquid crystaldisplay device, and a device and a method for testing a transparentelectrode of a flat panel device.

According to the above techniques, a micro processor determines whetherbus lines are disconnected (or shorted) or not by current level of thebus lines (or electrode lines) of the semiconductor to which a voltageis applied. The current level is detected automatically by a switchingmethod.

Although the current level is detected automatically by a switchingmethod, a detection of the current level should be made one by one fromeach bus line. Such inconvenience and prolongation of testing time arestill remaining unsolved.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a device and amethod for testing disconnection by grouping bus lines of asemiconductor device providing bus lines having field effect transistors(FET) of n units whose current ratios form a geometric series, groupingthe bus lines by n units, and measuring the sum of the current ratios byblock unit, to find the bus lines disconnected in the correspondingblock, and reduce the number of testing electrodes and testing time.

It is another object of the present invention to provide a device and amethod for testing disconnection by grouping bus lines of thesemiconductor device setting spaces between the testing electrodeswithout regards to spaces between the bus lines of the semiconductordevice, thereby standardizing the testing method.

To achieve the objects, the present invention proposes a device fortesting disconnection by grouping bus lines of a semiconductor devicecomprising:

switching devices connected to one end of each bus line of thesemiconductor device,

testing electrodes to which the above switching devices are connected,grouping by n units, and

electrodes for applying electric power to which the other end of eachbus line is connected to electrodes for applying electric power withgrouping by n unit, the n switching device whose current ratios areformed in a geometric series being provided, and the current flowingthrough testing electrodes via n bus lines being predetermined when thevoltage is applied to electrodes for applying an electric power.

As the other aspect of the present invention provides a method fortesting disconnection by grouping bus lines of a semiconductor devicecomprising the steps of:

applying a voltage to an electrode;

determining a sum of current flowing through n bus lines and n switchingdevices whose current ratios are formed in a geometric series by theabove electric power; and

said current being the sum of each current value flowing through n buslines, and distinguishing each of n bus lines by the current ratiosforming a geometric series, to be determined if n bus lines aredisconnected or not.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages and other objects of the present invention will beapparent in the following detailed description in connection with theaccompanying drawings, in which:

FIG. 1 is a detailed circuit diagram of a device for testingdisconnection by grouping bus lines of a semiconductor device inaccordance with a preferred embodiment of the present invention;

FIG. 2 is a detailed circuit diagram showing an example of applying adevice for testing disconnection by grouping bus lines of asemiconductor device in accordance with the preferred embodiment of thepresent invention; and

FIG. 3 is a circuit diagram showing a method for testing disconnectionof bus lines of a semiconductor device in accordance with theconventional art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a detailed circuit diagram of a device for testingdisconnection by grouping bus lines of a semiconductor device inaccordance with a preferred embodiment of the present invention;

FIG. 2 is a detailed circuit diagram showing an example of applying adevice for testing disconnection by grouping bus lines of asemiconductor device in accordance with the preferred embodiment of thepresent invention.

As shown in FIG. 1, in the inventive device for testing disconnection bygrouping bus lines of a semiconductor device, there are formedelectrodes GPAD1 to GPADk and DPAD1 to DPAD1 for applying electric powerrespectively on an upper area and on a left side of a liquid crystaldisplay panel 30, and field effect transistors (FET) respectively on alower area and on a right side of the above liquid crystal display panel30, the above FET is grouped by n units and testing electrodes D1 to Dkand D1 to D1 are connected to each block 11 to lk and 21 to 21, and gateelectrodes G1 to Gk and G1 to G1 are connected in common to n FETswithin each block 11 to 1k and 21 to 21.

A liquid crystal panel 30 is used as a semiconductor device according tothe preferred embodiment of the present invention. However, thetechnical scope of the present invention is not limited thereto. It canbe applied to another semiconductor devices demanding a test ofdisconnection of bus lines as DRAM, SRAM, and the like.

The following description is about the operation of the device and themethod for testing disconnection by grouping bus lines of thesemiconductor device according to the preferred embodiment of thepresent invention.

The voltage is applied to the electrodes GPAD1 to GPADk and DPAD1 toDPAD1 for applying electric power formed respectively on the upper areaand on the left side of the liquid crystal panel 30 and the circuitstarts operating. The current flows through each of bus lines grouped byn units and each FET connected to each bus line by the voltage appliedto the above electrodes GPAD1 to GPADk and DPAD1 to DAPD1 for applyingthe electric power.

At this time, the voltage is applied to the gate electrodes G1 to Gk andG1 to G1 within each block 11 to lk and 21 to 21 and the n FETs isturned on, and therefore the current can be measured from the testingelectrodes D1 to Dk and D1 to D1 within each block 11 to lk and 21 to21.

A variable voltmeter in FIG. 2 is to turn on the FET. The current flowsthrough each bus line and each FET by the voltage applied to theelectrode PAD1 and the current flowing through n bus lines can bedetermined by an ammeter A.

The FETs connected to each bus line in FIG. 1 are grouped by n unitswithin a block 11 to lk and 21 to 21 and the current ratios flowingthrough the n FETs F1 to Fn within each block 11 to lk and 21 to 21 forma geometric series. The current ratios of the n FETs are set to haverespectively different value of allowable current by regulating a ratioof width to length W/L of a channel region. The value of allowablecurrent between a drain and a source of an optional mth FET is can beexpressed as follows:

    i.sub.m =a.sup.m (`a` is a constant)

The current measured from the testing electrodes D1 to Dk and D1 to D1within each block 11 to lk and 21 to 21 is a sum of current flowingthrough the n bus lines and the n FETs, and the determined current canbe expressed as the sum of the geometric series. In case that one of nlines within each block 11 to lk and 21 to 21 is disconnected, thecurrent measured from the testing electrodes D1 to Dk and D1 to D1 isdetected excluding a current value of the line disconnected.

Accordingly, the disconnected line can be easily found if the bus linesdisconnected are mapped according to current values determined from thetesting electrodes D1 to Dk and D1 to D1. The current ratios of the nFETs are formed in a geometric series in order to easily find thedisconnected bus lines by determining the current value from the testingelectrodes D1 to Dk and D1 to D1.

For example, supposing n is 5 and a is 2, there are 5 FETs within oneblock, and current ratios of FETs are as follows:

    i1:i2:i3:i4:i5=1:2:4:8:16

If a proportional constant is K and there are no disconnected lineswithin the corresponding block, the current value i_(test) is measuredas 31K from a corresponding testing electrode. The changes of thecurrent values i_(test) are as follows: in case that

a first line is disconnected: 30K

a second line is disconnected: 29K

a third line is disconnected: 27K

second and fourth lines are disconnected: 21K

In any given cases, there can be determined by the current valuedetermined from the testing electrode which bus line is disconnected.

Since the current values are differently determined from thecorresponding block according to the disconnection of each bus line, thedisconnected lines can be found by analyzing the current values. Whenputting the present invention to practical use, there can be used ameasuring device to map disconnected bus lines according to currentvalue measured from the testing electrodes.

In case that the present invention is applied to a VGA, TFT, or LCDpanel having 480 gate lines and 1920 data lines, and the value of n is5, that is, five bus lines are grouped within one block, the test can bemade with electrodes decreased about 80 percent compared with theconventional art and 20 percent of the conventional testing time.Additionally, spaces between the testing electrodes are set withoutregards to spaces between the bus lines of the semiconductor devicebecause the number of the testing electrodes is decreased, tostandardize the testing method.

Although only a preferred embodiment and select modifications of theinvention have been disclosed and described, it is apparent that otherembodiments and modifications of the invention are possible within thescope of the appended claims.

What is claimed is:
 1. A device for testing for disconnection of buslines in a semiconductor device, comprising:switching means connected toone end of a group of n of said bus lines of said semiconductor device,said switching means having current ratios formed in a geometric series;at least one testing electrode connected to said switching means; and atleast one power electrode connected to said group of n of said bus linesfor applying electric power to said group of n of said bus line, suchthat a disconnection of one or more of said bus lines can be determinedaccording to a current flowing through said testing electrode.
 2. Thedevice according to claim 1, wherein said semiconductor device comprisesone of a liquid crystal display panel, a dynamic random access memoryand a static random access memory.
 3. The device according to claim 1,wherein said switching means is set to have current ratios formed in ageometric series by regulating ratios of width to lengths of channelregions of said switching means.
 4. A method for testing fordisconnection of bus lines in a semiconductor devices, comprising thesteps of:applying an electric power to said bus lines; and determining asum of current flowing through a group n of said bus lines, wherein anamount of current flowing each of said n bus lines is varied inaccordance with n switching means whose current ratios are formed in ageometric series; and distinguishing which of said n bus lines aredisconnected in accordance with said sum.
 5. A semiconductor devicehaving a plurality of bus lines, comprising:at least one electrodeconnected to at least one group of n of said bus lines for applyingelectric power to said at least one group of n of said bus lines;switching means for decreasing an amount of testing time required whiletesting for disconnection of said bus lines, said switching means beingconnected to each bus line in said at least one group of n of said buslines opposite said at least one electrode and having current ratiosformed in a geometric series; and at least one testing electrodeconnected to output terminals of said switching means.
 6. A device fortesting for disconnection of bus lines of a semiconductor device,comprising:switches having current ratios formed in a geometric series,each said switch being connected to a respective end of one of a groupof n of said bus lines; at least one testing electrode connected to saidswitches; and at least one power electrode connected to said group of nof said bus lines for applying electric power to said group of n of saidbus lines; wherein a disconnection of one or more of said bus lines canbe determined according to a current flowing through said testingelectrode.
 7. The device of claim 6, wherein said switches aretransistors, and said current ratios are formed by varying ratios ofwidths to lengths of channel regions of said transistors.